A Novel approach for Minimizing the Process Voltage Temperature Variation (PVT) Detector for Digital Converter Design

R. Shanmuga Sundaram^1,*, R. Mohanraj², S. Sasidevi¹

¹Assistant Professor Department of ECE, Knowledge Institute of Technology, Salem, Tamil Nadu, India.
     ²PG Scholar, Department of ECE, Knowledge Institute of Technology, Salem, Tamil Nadu, India.

Emails: rsece@kiot.ac.in; mohanraj487@gmail.com; ssdece@kiot.ac.in

Abstract

Time-to-digital converters (TDCs) are vital components in digital circuitry, crucial for synchronization and precise measurement, demanding high resolution and accuracy. This brief introduces a novel TDC designed in order to reduce the impact of fluctuations in process, voltage, and temperature. A process voltage temperature detector using an extra delay line that is optimized for locking situations is incorporated into the suggested TDC to distinguish PVT corners effectively. Implemented in a 90-nm process, on-silicon measurements reveal impressive performance achieving 30-ps resolution.

Keywords: D-flip-flip (DFF); Process voltage and temperature (PVT); PVT corner detector; Time-to-digital converter (TDC)