FPGA-Based Arithmetic Operator Implementation for FIR Filter Design Using FLUT Architecture

A. Arun^1,*, M. Thangavel², V. Kunavathi³

¹Assistant Professor, Department of ECE, Knowledge Institute of Technology, Salem, India

² Professor, Department of ECE, Knowledge Institute of Technology, Salem, India

³PG Scholar, Department of ECE, Knowledge Institute of Technology, Salem, India

Emails: aaece@kiot.ac.in; mtece@kiot.ac.in; kunavathi.venmani@gmail.com

Abstract

A Hardened adder with carry logic is commonly used in commercial field-programming gate arrays (FPGAs) to enhance arithmetic performance. The rapid expansion of portable multimedia players and communication systems has boosted the demand for high-speed, energy-efficient Digital Signal Processing (DSP) systems. The Finite Impulse Response (FIR) Filter is an essential component when developing an effective digital signal processing system. The use of a digital FIR filters is a key component in DSP. Digital multiplier and adders that are the most crucial arithmetic units used in FIR filters, determining the entire system's performance. As a result, the low-power design of systems has become a primary performance target. This paper also explores the influence of fLUTs and their interactions with toughened arithmetic. FLUTs (Fracturable-LUT) reduce the area by 15%, complementing the latency reductions offered by hardened arithmetic. An FIR filter based on the Carry-Look-ahead adder (CLA) and multipliers was proposed. The tentative results shows that the FIR filter using proposed multiplier method achieves less amount of delay and power reduction compared to conventional method.

Keywords: Carry Look-ahead Adder (CLA); Field Programmable Gate Array (FPGA); Fracturable Look-up table (FLUT)