Journal of Intelligent Systems and Internet of Things JISIoT 2690-6791 2769-786X 10.54216/JISIoT https://www.americaspg.com/journals/show/4178 2019 2019 Assistant Professor, Department of Mechatronics Engineering, Nehru Institute of Engineering and Technology, Coimbatore -641105, India Ravi Ravi Assistant Professor, Department of Aeronautical Engineering, Nehru Institute of Engineering and Technology, Coimbatore-641105, India S. Balaji Professor, Department of Electronics and Communication Engineering, Karpagam Institute of Technology, Coimbatore-641021, India Gokul. C. Associate Professor, Department of Electronics and Communication Engineering, Nehru Institute of Engineering and Technology, Coimbatore-641105, India K. Nagarajan Assistant Professor, Department of Electrical and Electronics Engineering, Nehru Institute of Engineering and Technology, Coimbatore-641105, India A. Arulkumar Assistant Professor, Department of Computer Science Engineering, Nehru Institute of Engineering and Technology, Coimbatore- 641105, India S. Venkatesh The rapid proliferation of edge-AI systems in IoT, autonomous robotics, and biomedical monitoring demands ultra-low-power, latency-aware intelligence that conventional deep neural networks struggle to provide due to heavy computation and memory overheads. Neuromorphic computing offers a promising biological-inspired alternative by processing information through sparse spiking events, enabling energy-efficient on-device learning and inference. This paper presents a neuromorphic VLSI accelerator based on a hybrid spiking neural architecture that combines Leaky-Integrate-and-Fire (LIF) neurons, adaptive threshold spiking units, and synaptic plasticity circuits to support both supervised and unsupervised learning modes at the edge. A hierarchical crossbar-memory topology integrated with non-volatile memristive synapses provides dense weight storage and real-time synaptic updates, reducing off-chip memory access by 78%. A pipelined event-driven computation engine and clock-gated spike scheduler minimize dynamic switching, achieving 61% reduction in power and 2.4× throughput improvement compared to conventional CMOS DNN accelerators. The proposed system performs dynamic visual-feature encoding, spike-based temporal fusion, and on-chip learning for anomaly and object detection tasks in low-power sensor nodes. Fabricated in 28-nm CMOS, the prototype achieves 0.29 mW power, 0.42 pJspike energy, and 94.3% inference accuracy, outperforming state-of-the-art neuromorphic platforms. Results demonstrate that hybrid spiking architectures integrated with VLSI-efficient plasticity circuits can deliver high-accuracy, self-adaptive AI within stringent edge constraints, enabling next-generation smart-sensing and autonomous micro-robotic intelligence. 2025 2025 426 435 10.54216/JISIoT.170228 https://www.americaspg.com/articleinfo/18/show/4178