International Journal of Wireless and Ad Hoc Communication

A novel honey pot deception trace back model, or honey pot IDS, is offered. The system is located on the server, which is the site of network intrusion deceptions. From there, it keeps an eye on all incoming traffic and uses nodes that carry out network weight age studies to continuously weigh the data. For every client connected to the server, it serves as a construct to look at the packet analysis and transmission path to which the IP processed the intrusion detection system. This LF-IDS detects intrusions using both anomaly-based and rule-based intrusion detection methods. By gathering and examining the packets from incoming traffic, the system initially collects data on the packet agent monitoring system. The trespasser is led to a honey pot that will be constructed as a mitigation site.

Road accidents and emergency services delay are the main significant issues. To overcome these issues need to develop a system. Efficient handling of accidents through the immediate detection and provide timely aid are more crucial. Accident detection and emergency system depends on IoT (Internet of things) with minimum delay are gaining significant attention towards industry and academic literature. Several researches are investigated using IOT technology to detect accidents. In this work, we proposed an effective accident detection method by employing five sensors not only to detect accident but also to report type of accident such as collision, no accident, roll over or fall off. In addition to that, the status of the accident is communicated to the IBM Watson Cloud platform. The incoming data received in the node red platform is integrated with the Google Maps to show location and other information about the accident that can be accessed by the hospital through website and also sending alert messages to victim acquaintances. In addition, two Machine Learning (ML) models based on K-Nearest Neighbor (KNN) model and the Naïve Bayes (NB) model are compared to find out the best accident detection model. It is noticed that the KNN model is the very effective ML model, which employed to know the accident status and also to enhance the system by providing patient’s details, a kill switch and sending messages often till acknowledgement is received.

This demand can be satisfied by cognitive radio (CR) technology thanks to the growing desire to utilize existing radio frequency bands more effectively. This paper suggests a hardware-efficient, very-large spectrum sensor. In cooperative cognitive radio networks, data fusion is not provided by a new-scale integration (VLSI) architecture. The cooperative method to spectrum sensing and management as a proposed concept uses approaches for data fusion to address the difficulties. Our VLSI system delivers high throughput with exceptional performance by combining the latest sensing algorithms with an effective hardware architecture. The overall performance of the spectrum and spectrum awareness are enhanced by the cooperative theoretical radio communication system. In order to enable the network to make judgements that can be modified utilizing combined data from scattered spectrum sensors, the study examines the integration of network fusion techniques. The suggested scheme's primary characteristics are its hardware efficiency, low power consumption, and real-time flexibility for changing spectrum conditions. Through simulations and comparison with existing methods, it is assessed. System performance is tracked, and the results indicate that faster and more accurate spectrum sensing is required in order to apply notions of spectrum sharing that make sense.

This work investigates into the meticulous analysis of the Transmission Gate (TG) based D Flip-Flop integrated with dynamic XOR-based clock gating, aimed at analyzing power consumption patterns and potential power savings across varying frequencies. While power consumption inherently reduces with smaller technology nodes, but this work demonstrates that dynamic clock gating can achieve further power savings, especially at higher operational frequencies and lower data activity. The outcomes represent a deeper understanding of power optimization techniques for sequential circuits. The analysis is performed using Cadence Virtuoso in a 90nm technology process, which determine the sophisticated interaction between design elements and power dynamics. Through comprehensive simulations, the power consumption of TG-based D flip-flops is meticulously examined across diverse technology nodes. Furthermore, the efficacy of integrating dynamic XOR-based clock gating to this flip-flop design is explored, unveiling its potential to yield substantial power savings. The research underscores the multifaceted nature of low-power design strategies, emphasizing their relevance across various hierarchies including system, architecture, circuit, and device levels. While advancements in technology nodes naturally lead to reduced power dissipation, this study illuminates the additional power-saving opportunities presented by the dynamic XOR-based clock gating approach. Especially, in this investigation highlights the significance of this approach particularly in scenarios characterized by higher frequencies of operation and low data activity. By leveraging dynamic XOR-based clock gating, the research showcases how power efficiency can be further augmented, offering insights into enhancing the overall energy efficiency of digital systems. In summary, this project provides a nuanced understanding of power dynamics in TG-based D flip-flops, shedding light on the intricate balance between technology advancements and innovative design methodologies for achieving optimal power efficiency. Through meticulous analysis and simulation, it unveils a promising avenue for realizing significant power savings, thereby contributing to the advancement of low-power design paradigms in modern digital systems.

A common symmetric key block cypher for protecting electronic data is called the Advanced Encryption Standard (AES). The implementation of the AES algorithm using Very-Large-Scale Integration (VLSI) is examined in this study. Cryptographic algorithms can be realised in hardware thanks to VLSI, which has advantages over software implementations in terms of increased processing speed and security. In this work, an AES block cypher core designed and implemented with VLSI techniques is described. We investigate various architectural designs to maximise performance indicators such as area, power consumption, and throughput. The trade-offs between different implementation options and design concerns for important components such as S-boxes will be covered. To illustrate the performance and usefulness of the implemented AES core, simulation results will be given. This paper examines the VLSI implementation of the Advanced Encryption Standard (AES), with a focus on image processing applications, even though it is essential for general data security. Effective on-chip encryption and decryption can be included into image processing systems by implementing the AES algorithm into specialised hardware circuits. Benefits of this VLSI design include enhanced performance over software-based solutions on resource-constrained image processing devices, the ability to encrypt images in real-time for secure transmission or storage, and the potential for reduced power usage for battery-powered applications.