International Journal of Wireless and Ad Hoc Communication

A Hardened adder with carry logic is commonly used in commercial field-programming gate arrays (FPGAs) to enhance arithmetic performance. The rapid expansion of portable multimedia players and communication systems has boosted the demand for high-speed, energy-efficient Digital Signal Processing (DSP) systems. The Finite Impulse Response (FIR) Filter is an essential component when developing an effective digital signal processing system. The use of a digital FIR filters is a key component in DSP. Digital multiplier and adders that are the most crucial arithmetic units used in FIR filters, determining the entire system's performance. As a result, the low-power design of systems has become a primary performance target. This paper also explores the influence of fLUTs and their interactions with toughened arithmetic. FLUTs (Fracturable-LUT) reduce the area by 15%, complementing the latency reductions offered by hardened arithmetic. An FIR filter based on the Carry-Look-ahead adder (CLA) and multipliers was proposed. The tentative results shows that the FIR filter using proposed multiplier method achieves less amount of delay and power reduction compared to conventional method.

Time-to-digital converters (TDCs) are vital components in digital circuitry, crucial for synchronization and precise measurement, demanding high resolution and accuracy. This brief introduces a novel TDC designed in order to reduce the impact of fluctuations in process, voltage, and temperature. A process voltage temperature detector using an extra delay line that is optimized for locking situations is incorporated into the suggested TDC to distinguish PVT corners effectively. Implemented in a 90-nm process, on-silicon measurements reveal impressive performance achieving 30-ps resolution.

In Cognitive Radio Networks (CRNs), Peak-to-Average-Power-Ratio (PAPR) reduction is crucial for mitigating distortion in signals while optimizing spectral efficiency. This work offers a novel strategy for effectively reducing that PAPR in CRN systems, especially when secondary users are incorporated, by utilizing VLSI (Very-Large-Scale Integration) design approaches. The proposed strategy investigates VLSI methods for PAPR reduction, such as Partial-Transmit-Sequence (PTS) techniques. The system is appropriate for CRN applications because it can accomplish real-time PAPR reduction while preserving low power consumption and compact size by implementing these approaches in VLSI hardware. This could entail particular strategies for controlling PAPR with secondary users, such as joint PAPR and spectrum sensing approaches, dynamic power allocation, or user scheduling algorithms. Utilizing the predetermined values of pilot tones, the suggested decoder investigates every possible combination of weighting variables to determine which combination the transmitter has chosen and employed. There appears to be no data rate loss with the proposed decoder since it does not require any more pilot tones. This study next gives a digital execution of the described PTS decoder and illustrates its low power qualities, as well as the design and the encoder required at the transmitter to operate the suggested system is being developed using VLSI. The suggested architecture makes it easier for SUs to integrate with CRNs seamlessly. It allows SUs to effectively take advantage of available spectrum opportunities while complying with CRN restrictions and reducing interference with primary users by tackling PAPR and spectrum sensing concurrently. Furthermore, the study discusses the difficulties of incorporating secondary users into CRNs while retaining PAPR management.

Creating images is one of the main focuses of digital image processing. There are multiple techniques to spot image fraud. This work proposes a new approach to detect attacks that mimic Copy-Move forgeries. The proposed method applies DWT on the input image to create a reduced dimensional representation of the image. After that, the compressed image is divided into overlapping blocks. After these blocks are sorted, phase correlation is utilized as a similarity criterion to find duplicate blocks. Due to DWT usage, the lowest-level picture representation is first employed for detection. This work also covers the examination of numerous limits that are imposed to the input image, and the results are used in the analysis that follows.

A recent study examined the applications of multiplication and division in video and image manipulation and there has been mention of machine learning. DSP blocks that function as high performance multipliers are given by FPGA providers. However routing lag time and inefficiencies, particularly for lower bit width multiplications, might emerge from the fixed placements and restricted number of these FPGA multipliers, raising power consumption. FPGA companies offer IP cores that are soft made especially for multiplication to solve this problem. Even if these IP cores have improved over time, they can yet be improved. This can be accomplished by creating low latency, accurate, and core multiplier topologies that maximize the space of FPGA and take advantage of its architectural characteristics, like rapid carry chains and look up table structures.  These architectures seek to improve overall efficiency by lowering the crucial path delay and multiplier resource consumption. Here a proposed method for building accurate and approximate signed and unsigned multipliers for an eight bit configuration is presented. This entails changing the LUT 6 architecture to use a one LUT 5 with multiplexers in place of a dual LUT 5 with multiplexers. Using Xilinx software, the design was built in Verilog HDL and synthesized. At the conclusion of the process, variables including area, delay and power were compared.

Artificial intelligence (AI) is becoming more and more necessary for devices, particularly for network edge image processing applications. Building Very-Large-Scale Integration (VLSI) systems that are specifically tuned for low power consumption and enable edge AI techniques for real-time image processing is the aim of this research. One of Edge AI's key characteristics is its ability to process data and make judgements instantly. Edge AI reduces latency by eliminating the need to move massive amounts of data from one location to the cloud. Quick response times are made feasible, which is essential for applications such as industrial automation and autonomous driving. The study will investigate hardware accelerators and approximation computing as efficient approaches to perform image processing algorithms on low-resource edge devices. If all created data were transferred to the cloud, the network infrastructures would be overwhelmed by the exponential growth in linked devices. Edge AI solves this issue by significantly reducing the amount of data that needs to be sent across the network by doing computations locally. This increases the scalability of AI systems and decreases operating costs associated with data transport. By using custom VLSI design, the project aims to achieve significant energy savings over traditional software-based solutions. This will pave the way for edge AI to be widely applied in battery-powered devices for longer battery life and tasks like object and picture identification.