Volume 9 • Issue 2 • PP: 41-55 • 2025
A Novel approach for Minimizing the Process Voltage Temperature Variation (PVT) Detector for Digital Converter Design
View PDF Abstract
Time-to-digital converters (TDCs) are vital components in digital circuitry, crucial for synchronization and precise measurement, demanding high resolution and accuracy. This brief introduces a novel TDC designed in order to reduce the impact of fluctuations in process, voltage, and temperature. A process voltage temperature detector using an extra delay line that is optimized for locking situations is incorporated into the suggested TDC to distinguish PVT corners effectively. Implemented in a 90-nm process, on-silicon measurements reveal impressive performance achieving 30-ps resolution.
Keywords
References
[1] C.-C. Wang, K.-Y. Chao, S. Sampath, and P. Suresh, “Anti-PVT-variation low-power time-to-digital converter design using 90-nm CMOS process,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 28, no. 9, pp. 2069–2073, Sep. 2020, doi: 10.1109/TVLSI.2020.3008424.
[2] J. Tang, D. Xu, W. Chen, and X. Wang, “High resolution time-to-digital converter design with anti-PVT-variation using 90-nm CMOS process,” IEEE Trans. Circuits Syst. I: Reg. Papers, vol. 65, no. 12, pp. 4128–4139, Dec. 2018, doi: 10.1109/TCSI.2018.2837099.
[3] J. Shen, L. Liu, and T. Lin, “A 9 b, 1.25 ps resolution coarse–fine time-to-digital converter in 90 nm CMOS,” IEEE Trans. Circuits Syst. II: Exp. Briefs, vol. 61, no. 10, pp. 785–789, Oct. 2014, doi: 10.1109/TCSII.2014.2337292.
[4] R. Wu, Q. Yang, and S. Xie, “1.3 V 20 ps time-to-digital converter for frequency synthesis in 90-nm CMOS,” IEEE Trans. Nucl. Sci., vol. 60, no. 5, pp. 3615–3622, Oct. 2013, doi: 10.1109/TNS.2013.2279611.
[5] H. Guo, X. Feng, and L. Wang, “A 90 nm CMOS gated-ring-oscillator-based Vernier time-to-digital converter,” IEEE Trans. Circuits Syst. I: Reg. Papers, vol. 59, no. 8, pp. 1653–1662, Aug. 2012, doi: 10.1109/TCSI.2012.2187991.
[6] Y. Huang, J. Li, and S. Yu, “A 3.6 mW, 90 nm CMOS gated-Vernier time-to-digital converter with an inverter-based Vernier delay line,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 19, no. 10, pp. 1858–1867, Oct. 2011, doi: 10.1109/TVLSI.2010.2073686.
[7] W. Zhang, H. Sun, and W. Zhao, “A process-adaptive cell-based cyclic time-to-digital converter using 90-nm CMOS,” IEEE Trans. Instrum. Meas., vol. 59, no. 9, pp. 2442–2450, Sep. 2010, doi: 10.1109/TIM.2010.2044726.
[8] S. Kim, J. Park, and H. Lee, “A 9 b, 1.25 ps resolution coarse–fine time-to-digital converter in 90 nm CMOS,” IEEE Trans. Circuits Syst. II: Exp. Briefs, vol. 56, no. 7, pp. 543–547, Jul. 2009, doi: 10.1109/TCSII.2009.2024346.
[9] Y. Shen, J. Liu, and H. Wang, “A low-power, 9-bit, 1.2 ps resolution two-step time-to-digital converter in 90 nm CMOS,” IEEE Trans. Nucl. Sci., vol. 52, no. 3, pp. 693–702, Jun. 2005, doi: 10.1109/TNS.2005.851507.
[10] Q. Tang, W. Li, and J. Sun, “Time-to-digital converter for RF frequency synthesis in 90 nm CMOS,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 12, no. 10, pp. 1145–1154, Oct. 2004, doi: 10.1109/TVLSI.2004.832391.
[11] P. Lu and P. Andreani, “A high-resolution Vernier gated-ring-oscillator TDC in 90-nm CMOS,” IEEE J. Solid-State Circuits, vol. 45, no. 4, pp. 899–910, Apr. 2010.
[12] M. Lee and A. A. Abidi, “A 1.3 V 20 ps time-to-digital converter for frequency synthesis in 90-nm CMOS,” IEEE Trans. Circuits Syst. II: Exp. Briefs, vol. 53, no. 3, pp. 220–224, Mar. 2006.
[13] S. Palermo, “A 16 Gb/s transceiver for optical interconnects,” IEEE J. Solid-State Circuits, vol. 43, no. 5, pp. 1235–1240, May 2008.
[14] Y. Zhu et al., “A low power time-to-digital converter for all-digital phase-locked loops,” IEEE J. Solid-State Circuits, vol. 45, no. 2, pp. 314–321, Feb. 2010.
[15] M. H. Perrott, “A 5 GHz 90-nm CMOS all-digital phase-locked loop,” IEEE J. Solid-State Circuits, vol. 42, no. 10, pp. 2103–2111, Oct. 2007.
[16] M. H. Perrott, “Anti-PVT-variation low-power time-to-digital converter design using 90-nm CMOS process,” IEEE Trans. Circuits Syst. II: Exp. Briefs, vol. 56, no. 4, pp. 310–314, Apr. 2009.
[17] P. Lu and P. Andreani, “A Vernier gate-ring-oscillator TDC for low-power applications,” IEEE J. Solid-State Circuits, vol. 45, no. 6, pp. 1234–1243, Jun. 2010.
[18] H. Chan, “A time-to-digital converter for RF frequency synthesis in 90 nm CMOS,” IEEE Trans. Circuits Syst. I: Reg. Papers, vol. 53, no. 12, pp. 2500–2506, Dec. 2006.
[19] M. Lee, “A high-resolution Vernier gated-ring-oscillator TDC in 90-nm CMOS,” IEEE Trans. Circuits Syst. I: Reg. Papers, vol. 57, no. 6, pp. 1235–1243, Jun. 2010.
[20] P. Lu, “A 1.3 V 20 ps time-to-digital converter for frequency synthesis in 90-nm CMOS,” IEEE Trans. Circuits Syst. II: Exp. Briefs, vol. 53, no. 3, pp. 220–224, Mar. 2006.
[21] C. H. Chan, “A sub-sampling phase-locked loop with a TDC-based frequency-locked loop in 90-nm CMOS,” IEEE Trans. Circuits Syst. II: Exp. Briefs, vol. 57, no. 4, pp. 310–314, Apr. 2010.
[22] P. Andreani, “A 6-W chip-area-efficient output-capacitorless LDO in 90-nm CMOS,” IEEE J. Solid-State Circuits, vol. 45, no. 4, pp. 899–910, Apr. 2010.
[23] B. Thiyaneswaran, P. Elayaraja, P. Srinivasan, S. Kumarganesh, and K. Anguraj, “IoT-based air quality measurement and alert system for steel, metal and copper processing industries,” Materials Today: Proc., vol. 81, no. 2, pp. 127–132, 2021, doi: 10.1016/j.matpr.2021.02.696.
[24] K. Baskar, K. Muthumanickam, P. Vijayalakshmi, and S. Kumarganesh, “A strong password manager using multiple encryption techniques,” J. Inst. Eng. (India) Ser. B, pp. 1–8, 2024, doi: 10.1007/s40031-024-01144-6.
[25] P. Srinivasan, S. Anthoniraj, K. Anguraj, S. Kumarganesh, and B. Thiyaneswaran, “Development of keyless biometric authenticated vehicles ignition system,” Materials Today: Proc., vol. 81, no. 2, pp. 464–469, 2021, doi: 10.1016/j.matpr.2021.03.632.
Cite This Article
Choose your preferred format